In modern day digital telecommunications, the backbone for a packet data network is typically a T-1 Carrier digital transmission line or its equivalent. A T-1 Carrier digital transmission line operates at a bit rate of 1.544 megabits per second, providing a total bandwidth of 1,544 MHz, and normally supports 24 time division multiplexed digital DS0 channels. Each of these 24 digital DS0 channels has an effective bit rate of 64 kilobits per second, providing a bandwidth of 64 KHz each. A typical packet network includes a plurality of separate packet network nodes, coupled to one another by T-1 Carrier digital transmission lines or their equivalent.
A packet network node generally operates to assign a plurality of T-1 digital DS0 channels to form a broader band packet data transmission channel, leaving the remaining digital channels to be used either by additional packet data transmission channels or as such separate and distinct time division multiplex circuit switched channels as voice or channels in the form of multiple voice channels. Because such additional time division multiplex channels as separate voice channels or channels formed by multiple voice channels may sometimes be inactive, it can be useful to make their unused bandwidth available temporarily to increase the bandwidths available to active packet data transmission channels. In the past, such temporarily unused bandwidth has been reallocated either synchronously or asynchronously.
In synchronous reallocation, frame random access memories (often called, more simply, frame RAMs) containing digital channel allocation information in packet network nodes at both ends of a T-1 Carrier transmission line need to be reconfigured simultaneously in order to ensure continuous flow of data. In such arrangements, a second frame is typically developed with all changes incorporated within it at both source and destination nodes before a signal from the source node to the destination node specifies when to change the frame. Synchronous reconfiguration tends to be highly complex and demanding of memory, particularly when more than one packet channel is involved.
Past asynchronous reconfiguration techniques require that internodal packet data transmission be interrupted each time a frame RAM reconfiguration at opposite ends of the transmission system takes place. Typically, packet data buffering is required each time the frame is reconfigured. Such asynchronous bandwidth switching also becomes an increasingly complex process as additional digital channels are reallocated, particularly if more than one packet channel is involved.